The present invention pertains in general to packaging of semiconductor components, and more particularly, to packaging of multiple semiconductor die in a laminated substrate with an interconnect layer formed in a deposited overlay structure.
Interconnection of electronic devices has become a significant factor in determining the performance of electronic systems in recent years. This is due in part to the trend toward higher device integration, i.e., large scale integrated circuits with several million active transistor elements, sub-micron feature sizes and I/O pinouts approaching 400-500 connections, along with the associated increase in silicon real estate size, typically greater than 0.50 inches, and power dissipations of greater than five watts per IC. These factors certainly pose major technology problems for the electronics packaging engineer, especially in the area of single chip packaging. Present IC packaging design approaches, material systems, and technologies for single chip packaging have become, in the high-end integrated circuits, significant performance differentiators and, as such, comprise major product differentiators.
The emerging need to integrate off-chip interconnect with tailored electrical characteristics of controlled impedance transmission lines, low-loss power and ground distribution networks and minimal signal paths has driven the present leading edge subsystem components to consider a form of electronics packaging known within the industry as Multi-Chip Modules, or MCM. An MCM typically constitutes the ability to package multiple bare ICs in a single subsystem package, where chip-to-chip interconnect is supported by one of a number of high performance interconnect approaches internal to the next system packaging level interface. There are at present three major classes of MCM packaging approaches.
The first class of MCM has come to be known as MCM-L, where the xe2x80x9cLxe2x80x9d stands for Laminate technology. This approach typically consists of an extension of standard printed wiring board technology that supports fine dimension surface features to enable 6-10 mil lead pitch interfaces for a perimeter pad device to provide for the interconnect. Electrical connections for a plurality of ICs are generally made with a Tape Automated Bonding (TAB) lead interface from the outer perimeter bond pads on the device to a fine lead pitch perimeter pad interfaced on the Laminate technology interconnect. When multiple bare ICs having TAB lead frames attached to the I/O bond pads are interconnected with this approach, an MCM system is created; hence, the term MCM-L. Alternate methods of device-to-Laminate interconnect electrical connection can be used. For example, bare chip wire bond connections and either solder bump or electrically conductive adhesive bonds are in use or in development within the industry. This technology has become accepted as a low-cost manufacturing approach for the low-to-mid range performance (typically 20-70 MHz clock frequency) products and has the significant advantages of availability, low-cost, low-risk and the ability to leverage existing packaging technology into the emerging high-volume MCM packaging applications.
The second class of MCM packaging technology is known as MCM-C. This approach is an extension of both the hybrid practice, where xe2x80x9cthick filmxe2x80x9d metallizations can be screen printed and then fired in multiple layers on a ceramic substrate, and the multi-layered co-fired single chip packaging technologies, where screened metallizations are printed on ceramic in the xe2x80x9cgreen tapexe2x80x9d or prefired state and the ceramic tape and metallization are cured in a single process. In either case, an interconnect of several layers is formed on a ceramic substrate, which can also serve as a package to interconnect to the next system level, and a plurality of ICs can then be connected to this wiring structure by a variety of techniques. Among the methods for IC connection that are utilized are: wire bond, flip chip solder bump, TAB, thermal compression bond, TAB solder interface and electrically conductive polymer adhesive. This technology has the advantage of significant leverage of an installed base of ceramic interconnect manufacturing due to its reliance on extensions of single chip packaging technologies and hybrid interconnect technologies. However, there are penalties in interconnect wiring densities due to the limitations in feature sizes that can be achieved, and in general the electrical performance characteristics of the ceramic wiring substrate, which present limitations not suitable for leading technology IC interconnect.
The third class of MCM packaging technology is known as MCM-D, where xe2x80x9cDxe2x80x9d stands for Deposited (metallization). This approach leverages thin film process techniques that are typically extensions of IC manufacturing processes. Because of this, interconnect feature sizes much finer than the present art MCM-L or MCM-C features are achievable. MCM-D interconnects are typically constructed of dielectric layers of polyimide based materials with either aluminum or copper and barrier metal conductors in multiple layer structures. These thin film multi-layer MCM-D wiring interconnects are built using a variety of materials for mechanical substrates, which provide a manufacturing tooling plate for processing, and mechanical and thermal structures for next level package interface. Substrate materials that can be used include silicon, ceramics, glass and metal matrix composite materials. MCM-D thin film interconnects generally display the best attributes of electrical performance characteristics in the smallest packaging size and thermal penalty attributes. However, they also exhibit the highest manufacturing costs at present and due to this, are limited for consideration to only the interconnect applications that demand the highest electrical and mechanical packaging solutions.
The present invention disclosed and claimed herein comprises a multi-chip integrated circuit package. The package includes a substrate having upper and lower surfaces and being fabricated from a polymer material with a lower electrically conductive layer disposed on the lower surface with a first thickness. The substrate has a lower surface disposed on a lower side thereof A plurality of cavities are formed on the upper surface of the substrate for receiving integrated circuit chips and being of sufficient depth that, when the integrated circuit chips are disposed therein, the upper surface of the integrated circuit chips disposed therein are substantially co-planar with the upper surface of the substrate. A layer of interconnect laminate film is disposed over the upper surface of the substrate and the integrated circuit chips with a plurality of via openings disposed therein. The via openings are disposed such that they expose select ones of the bonding pads. A pattern of interconnect conductors is disposed on the top of the laminate film so as to extend between at least some of the via openings and provide electrical connections between select ones of the bonding pads and the pattern of interconnect conductors. The pattern of interconnect conductors has a thickness substantially less than the first thickness.
In another aspect of the present invention, the substrate is comprised of a first polymer layer and a second polymer layer. The first polymer layer has a first conductive layer disposed on the upper surface thereof and is operable to contain a plurality of cavitities. The cavities extend from the upper surface of the first conductive layer to the lower surface of the first polymer layer. The second polymer layer has a second conductive layer disposed on the upper surface thereof and a third conductive layer disposed on the lower surface thereof, the third conductive layer comprising the lower layer of the substrate. An adhesive layer adhesively attaches the lower surface of the first polymer layer to the upper surface of the second conductive layer. The sheet resistance of at least one of the second and third conductive layers is substantially lower than the sheet resistance of the pattern of interconnection conductors.
In a further aspect of the present invention, an input/output connector is provided having a body support on the substrate with a plurality of substrate pins and a plurality of system pins. The substrate pins are operable to be inserted into select ones of plated-through holes connected between the upper and lower layers of the substrate, of which select ones of the plated-through holes are isolated from the third conductive layer, and which plated-through holes have an input/output function associated therewith. The system pins are operable to interface between the substrate pins and an external system, the substrate pins operating in a removable manner with respect to the external system. The system pins allow signals and power supply voltages to be provided to the plated-through holes and, subsequently, to the pattern of interconnection conductors. In one embodiment, the third conductive layer comprises a ground plane or a power supply plane.